A high-speed, low-power conditional push-pull pulsed latches with split paths technology

A 65-nm CMOS technology is used in this paper for introducing a novel class pulsed latches. It is having topology of conditional push-pull pulsed latch and is designed based on two split paths with conditional pulse generator. The pulse generator is the main difference, which can be either shared (CSP 3 L) or not (CP 3 L). Proposed topology outperforms than TGPL and it is very fast. The energy efficiency of the proposed latch is very high when compared to other pulsed latches. Indeed, a 2.3× improvement in ED 3 product (energy × delay 3 ) over TGPL was found for designs targeting minimum ED 3 . The characteristics of the proposed pulsed latches beyond the conventional latches whatever proposed. The main idea is to adopt a push–pull output stage, which is driven by two split paths for rise and fall output transitions, with the explicit aim of reducing both the path effort and the